AXI4UART.scala (a3e876088a970fa1ef84da031edd9363593d0e9f) AXI4UART.scala (3c02ee8f82edea481fa8336c7f54ffc17fafba91)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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16
17package device
18
19import chisel3._
20import chisel3.util._
21import chipsalliance.rocketchip.config.Parameters
22import freechips.rocketchip.diplomacy.AddressSet
23import utils._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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16
17package device
18
19import chisel3._
20import chisel3.util._
21import chipsalliance.rocketchip.config.Parameters
22import freechips.rocketchip.diplomacy.AddressSet
23import utils._
24import utility._
24import difftest._
25
26class AXI4UART
27(
28 address: Seq[AddressSet]
29)(implicit p: Parameters)
30 extends AXI4SlaveModule(address, executable = false, _extra = new UARTIO)
31{

--- 22 unchanged lines hidden --- 		25import difftest._
26
27class AXI4UART
28(
29 address: Seq[AddressSet]
30)(implicit p: Parameters)
31 extends AXI4SlaveModule(address, executable = false, _extra = new UARTIO)
32{

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