AXI4IntrGenerator.scala (f320e0f01bd645f0a3045a8a740e60dd770734a9) AXI4IntrGenerator.scala (151b6d601105e00bc5fd3d486aad344137a5605a)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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19import chisel3._
20import chisel3.util._
21import chipsalliance.rocketchip.config.Parameters
22import freechips.rocketchip.diplomacy.AddressSet
23import utils._
24
25// we support 256 interrupt bits by default
26class IntrGenIO extends Bundle {
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 10 unchanged lines hidden (view full) ---

19import chisel3._
20import chisel3.util._
21import chipsalliance.rocketchip.config.Parameters
22import freechips.rocketchip.diplomacy.AddressSet
23import utils._
24
25// we support 256 interrupt bits by default
26class IntrGenIO extends Bundle {
27 val intrVec = Output(UInt(256.W))
27 val intrVec = Output(UInt(64.W))
28}
29
30class AXI4IntrGenerator
31(
32 address: Seq[AddressSet]
33)(implicit p: Parameters)
34 extends AXI4SlaveModule(address, executable = false, _extra = new IntrGenIO)
35{
36
37 override lazy val module = new AXI4SlaveModuleImp(this){
38
28}
29
30class AXI4IntrGenerator
31(
32 address: Seq[AddressSet]
33)(implicit p: Parameters)
34 extends AXI4SlaveModule(address, executable = false, _extra = new IntrGenIO)
35{
36
37 override lazy val module = new AXI4SlaveModuleImp(this){
38
39 val intrReg = RegInit(VecInit(Seq.fill(8)(0.U(32.W))))
39 val intrGenRegs = RegInit(VecInit(Seq.fill(8)(0.U(32.W))))
40
41 // 0x0 - 0x8
42 val intrReg = VecInit(intrGenRegs.take(2))
43 // 0x8 - 0x10
44 val randEnable = VecInit(intrGenRegs.slice(2, 4))
45 // 0x10
46 val randMask = intrGenRegs(4)
47 val randCounter = intrGenRegs(5)
48 val randThres = intrGenRegs(6)
49
50 val randomPosition = LFSR64()(5, 0)
51 val randomCondition = randCounter === randThres && randEnable(randomPosition(5))(randomPosition(4, 0))
52 randCounter := randCounter + 1.U
53 when (randomCondition) {
54 intrGenRegs(randomPosition(5)) := intrReg(randomPosition(5)) | UIntToOH(randomPosition(4, 0))
55 }
56
40 io.extra.get.intrVec := Cat(intrReg.reverse)
41
57 io.extra.get.intrVec := Cat(intrReg.reverse)
58
42 when (in.w.fire()) {
43 intrReg(waddr(4, 2)) := in.w.bits.data(31, 0)
59 when (in.w.fire) {
60 randThres := LFSR64() & randMask
61 intrGenRegs(waddr(4, 2)) := in.w.bits.data(31, 0)
62 randCounter := 0.U
44 }
45
46 in.r.bits.data := intrReg(raddr)
47 }
48}
63 }
64
65 in.r.bits.data := intrReg(raddr)
66 }
67}