AXI4IntrGenerator.scala (3c02ee8f82edea481fa8336c7f54ffc17fafba91) AXI4IntrGenerator.scala (8891a219bbc84f568e1d134854d8d5ed86d6d560)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device
18
19import chisel3._
20import chisel3.util._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device
18
19import chisel3._
20import chisel3.util._
21import chipsalliance.rocketchip.config.Parameters
21import org.chipsalliance.cde.config.Parameters
22import freechips.rocketchip.diplomacy.AddressSet
23import utils._
24import utility._
25
26// we support 256 interrupt bits by default
27class IntrGenIO extends Bundle {
28 val intrVec = Output(UInt(64.W))
29}

--- 53 unchanged lines hidden --- 		22import freechips.rocketchip.diplomacy.AddressSet
23import utils._
24import utility._
25
26// we support 256 interrupt bits by default
27class IntrGenIO extends Bundle {
28 val intrVec = Output(UInt(64.W))
29}

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