Default.yml (69b78670068a0a6f0fb634fc02c24fc772838119) Default.yml (53bd4e1cb2bbe049a6887a8f3c75c296803c14b0)
1PmemRanges:
2 - { lower: 0x80000000, upper: 0x80000000000 }
3
4PMAConfigs:
5 - { base_addr: 0x0, range: 0x1000000000000, a: 3 }
6 - { base_addr: 0x80000000000, c: true, atomic: true, a: 1, x: true, w: true, r: true }
7 - { base_addr: 0x80000000, a: 1, w: true, r: true }
8 - { base_addr: 0x3A000000, a: 1 }
9 - { base_addr: 0x39002000, a: 1, w: true, r: true }
10 - { base_addr: 0x39000000, a: 1, w: true, r: true }
11 - { base_addr: 0x38022000, a: 1, w: true, r: true }
12 - { base_addr: 0x38021000, a: 1, x: true, w: true, r: true }
13 - { base_addr: 0x30010000, a: 1, w: true, r: true }
14 - { base_addr: 0x20000000, a: 1, x: true, w: true, r: true }
15 - { base_addr: 0x10000000, a: 1, w: true, r: true }
16 - { base_addr: 0 }
17
18EnableCHIAsyncBridge: true
19
1PmemRanges:
2 - { lower: 0x80000000, upper: 0x80000000000 }
3
4PMAConfigs:
5 - { base_addr: 0x0, range: 0x1000000000000, a: 3 }
6 - { base_addr: 0x80000000000, c: true, atomic: true, a: 1, x: true, w: true, r: true }
7 - { base_addr: 0x80000000, a: 1, w: true, r: true }
8 - { base_addr: 0x3A000000, a: 1 }
9 - { base_addr: 0x39002000, a: 1, w: true, r: true }
10 - { base_addr: 0x39000000, a: 1, w: true, r: true }
11 - { base_addr: 0x38022000, a: 1, w: true, r: true }
12 - { base_addr: 0x38021000, a: 1, x: true, w: true, r: true }
13 - { base_addr: 0x30010000, a: 1, w: true, r: true }
14 - { base_addr: 0x20000000, a: 1, x: true, w: true, r: true }
15 - { base_addr: 0x10000000, a: 1, w: true, r: true }
16 - { base_addr: 0 }
17
18EnableCHIAsyncBridge: true
19
20L2CacheConfig: { size: 1 MB, ways: 8, inclusive: true, banks: 4, tp: true }
20L2CacheConfig: { size: 1 MB, ways: 8, inclusive: true, banks: 4, tp: true, enableFlush: false }
21
22L3CacheConfig: { size: 16 MB, ways: 16, inclusive: false, banks: 4 }
23
24HartIDBits: 6
25
26DebugAttachProtocals: [JTAG]
27
28DebugModuleParams:

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65
66XSTopPrefix: ""
67
68EnableDFX: true
69
70EnableSramCtl: false
71
72EnableCHINS: false
21
22L3CacheConfig: { size: 16 MB, ways: 16, inclusive: false, banks: 4 }
23
24HartIDBits: 6
25
26DebugAttachProtocals: [JTAG]
27
28DebugModuleParams:

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65
66XSTopPrefix: ""
67
68EnableDFX: true
69
70EnableSramCtl: false
71
72EnableCHINS: false
73
74CHIAddrWidth: 48