| README.md (b8bf926cfdaf9d9b342a51422dbe4f280579c73f) | README.md (2f256e1de47c0fa510ed811cb0cf2518eeca17c9) |
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| 1# XiangShan 2 3XiangShan (香山) is an open-source high-performance RISC-V processor project. 4 5Detailed documents will be released in the near future. 6 7Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences. 8 --- 63 unchanged lines hidden (view full) --- 72* Install [Verilator](https://verilator.org/guide/latest/), the open-source Verilog simulator. 73* Run `make emu` to build the C++ simulator `./build/emu` with Verilator. 74* Refer to `./build/emu --help` for run-time arguments of the simulator. 75* Refer to `Makefile` and `verilator.mk` for more information. 76 77Example: 78```bash 79make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10 | 1# XiangShan 2 3XiangShan (香山) is an open-source high-performance RISC-V processor project. 4 5Detailed documents will be released in the near future. 6 7Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences. 8 --- 63 unchanged lines hidden (view full) --- 72* Install [Verilator](https://verilator.org/guide/latest/), the open-source Verilog simulator. 73* Run `make emu` to build the C++ simulator `./build/emu` with Verilator. 74* Refer to `./build/emu --help` for run-time arguments of the simulator. 75* Refer to `Makefile` and `verilator.mk` for more information. 76 77Example: 78```bash 79make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10 |
| 80./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin | 80./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so |
| 81``` 82 83 84 85## Acknowledgement 86 87In the development of XiangShan, some sub-modules from open source community are employed. All relavant usage is listed below. 88 89| Sub-module | Source | Detail | 90| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ | 91| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | We enhance the function and the timing of the original module, finally turning it into a Cache generator that can be configured as L2/LLC. | 92| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. | 93| FPU | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | We use Berkeley-hardfloat as our FPU and implement a SRT-4 div/sqrt unit for it. Additionally, we split the FMA pipeline to optimize the timing. | 94 95We are grateful for the support of the open source community and encourage other open source projects to reuse our code within the scope of the [license](LICENSE). 96 | 81``` 82 83 84 85## Acknowledgement 86 87In the development of XiangShan, some sub-modules from open source community are employed. All relavant usage is listed below. 88 89| Sub-module | Source | Detail | 90| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ | 91| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | We enhance the function and the timing of the original module, finally turning it into a Cache generator that can be configured as L2/LLC. | 92| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. | 93| FPU | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | We use Berkeley-hardfloat as our FPU and implement a SRT-4 div/sqrt unit for it. Additionally, we split the FMA pipeline to optimize the timing. | 94 95We are grateful for the support of the open source community and encourage other open source projects to reuse our code within the scope of the [license](LICENSE). 96 |