| README.md (a2c5157668cef4d050bc976fb5c45faa6bfe214a) | README.md (8c0a01afbe82229c17d6d4d0063f93c3171d8843) |
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| 1# XiangShan 2 3XiangShan (香山) is an open-source high-performance RISC-V processor project. 4 5Detailed documents will be released in the near future. | 1# XiangShan 2 3XiangShan (香山) is an open-source high-performance RISC-V processor project. 4 5Detailed documents will be released in the near future. |
| 6中文说明[在此](README-ZH-HANS.md)。 |
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| 6 7Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences. 8 9 10 11## === Tutorial is Coming! === 12 13A tutorial on XiangShan is held at RISC-V World Conference China 2021 in June. Multiple technical reports will be included in the conference as well. Stay tuned! 14 15For more information, please refer to [this link](https://openxiangshan.github.io). 16 17 18 19## Architecture 20 | 7 8Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences. 9 10 11 12## === Tutorial is Coming! === 13 14A tutorial on XiangShan is held at RISC-V World Conference China 2021 in June. Multiple technical reports will be included in the conference as well. Stay tuned! 15 16For more information, please refer to [this link](https://openxiangshan.github.io). 17 18 19 20## Architecture 21 |
| 21The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this [branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June, 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on master branch. | 22The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this [branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on the master branch. |
| 22 23The micro-architecture overview is shown below. 24 25 26 27 28 29## Sub-directories Overview --- 40 unchanged lines hidden (view full) --- 70### Run with simulator 71 72* Install [Verilator](https://verilator.org/guide/latest/), the open-source Verilog simulator. 73* Run `make emu` to build the C++ simulator `./build/emu` with Verilator. 74* Refer to `./build/emu --help` for run-time arguments of the simulator. 75* Refer to `Makefile` and `verilator.mk` for more information. 76 77Example: | 23 24The micro-architecture overview is shown below. 25 26 27 28 29 30## Sub-directories Overview --- 40 unchanged lines hidden (view full) --- 71### Run with simulator 72 73* Install [Verilator](https://verilator.org/guide/latest/), the open-source Verilog simulator. 74* Run `make emu` to build the C++ simulator `./build/emu` with Verilator. 75* Refer to `./build/emu --help` for run-time arguments of the simulator. 76* Refer to `Makefile` and `verilator.mk` for more information. 77 78Example: |
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| 78```bash 79make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10 80./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so 81``` 82 | 80```bash 81make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10 82./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so 83``` 84 |
| 83 84 | |
| 85## Acknowledgement 86 | 85## Acknowledgement 86 |
| 87In the development of XiangShan, some sub-modules from open source community are employed. All relevant usage is listed below. | 87In the development of XiangShan, some sub-modules from the open-source community are employed. All relevant usage is listed below. |
| 88 89| Sub-module | Source | Detail | 90| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ | 91| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | We enhance the function and the timing of the original module, finally turning it into a Cache generator that can be configured as L2/LLC. | 92| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. | | 88 89| Sub-module | Source | Detail | 90| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ | 91| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | We enhance the function and the timing of the original module, finally turning it into a Cache generator that can be configured as L2/LLC. | 92| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. | |
| 93| FPU | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | We use Berkeley-hardfloat as our FPU and implement a SRT-4 div/sqrt unit for it. Additionally, we split the FMA pipeline to optimize the timing. | | 93| FPU | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | We use Berkeley-hardfloat as our FPU and implement an SRT-4 div/sqrt unit for it. Additionally, we split the FMA pipeline to optimize the timing. | |
| 94 | 94 |
| 95We are grateful for the support of the open source community and encourage other open source projects to reuse our code within the scope of the [license](LICENSE). | 95We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the [license](LICENSE). |
| 96 | 96 |