README.md (708ceed4afe43fb0ea3a52407e46b2794c573634) README.md (2d02df72f8861d29bc63c99542df0e849f9453f7)
1# XiangShan
2
3XiangShan (香山) is an open-source high-performance RISC-V processor project.
4
5中文说明[在此](readme.zh-cn.md)。
6
7Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences.
8

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85
86Example:
87
88```bash
89make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10
90./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so
91```
92
1# XiangShan
2
3XiangShan (香山) is an open-source high-performance RISC-V processor project.
4
5中文说明[在此](readme.zh-cn.md)。
6
7Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences.
8

--- 76 unchanged lines hidden (view full) ---

85
86Example:
87
88```bash
89make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10
90./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so
91```
92
93## Troubleshooting Guide
94
95[Troubleshooting Guide](https://github.com/OpenXiangShan/XiangShan/wiki/Troubleshooting-Guide)
96
93## Acknowledgement
94
95In the development of XiangShan, some sub-modules from the open-source community are employed. All relevant usage is listed below.
96
97| Sub-module | Source | Detail |
98| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ |
99| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | We enhance the function and the timing of the original module, finally turning it into a Cache generator that can be configured as L2/LLC. |
100| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. |
101| FPU | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | We use Berkeley-hardfloat as our FPU and implement an SRT-4 div/sqrt unit for it. Additionally, we split the FMA pipeline to optimize the timing. |
102
103We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the [license](LICENSE).
104
97## Acknowledgement
98
99In the development of XiangShan, some sub-modules from the open-source community are employed. All relevant usage is listed below.
100
101| Sub-module | Source | Detail |
102| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ |
103| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | We enhance the function and the timing of the original module, finally turning it into a Cache generator that can be configured as L2/LLC. |
104| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. |
105| FPU | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | We use Berkeley-hardfloat as our FPU and implement an SRT-4 div/sqrt unit for it. Additionally, we split the FMA pipeline to optimize the timing. |
106
107We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the [license](LICENSE).
108