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| 1# XiangShan 2 3XiangShan (香山) is an open-source high-performance RISC-V processor project. 4 5中文说明[在此](readme.zh-cn.md)。 6 7Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences. 8 --- 14 unchanged lines hidden (view full) --- 23Zhihu/知乎：[香山开源处理器](https://www.zhihu.com/people/openxiangshan) 24 25Weibo/微博：[香山开源处理器](https://weibo.com/u/7706264932) 26 27You can contact us through [our mail list](mailto:[email protected]). All mails from this list will be archived to [here](https://www.mail-archive.com/[email protected]/). 28 29## Architecture 30 | 1# XiangShan 2 3XiangShan (香山) is an open-source high-performance RISC-V processor project. 4 5中文说明[在此](readme.zh-cn.md)。 6 7Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences. 8 --- 14 unchanged lines hidden (view full) --- 23Zhihu/知乎：[香山开源处理器](https://www.zhihu.com/people/openxiangshan) 24 25Weibo/微博：[香山开源处理器](https://weibo.com/u/7706264932) 26 27You can contact us through [our mail list](mailto:[email protected]). All mails from this list will be archived to [here](https://www.mail-archive.com/[email protected]/). 28 29## Architecture 30 |
| 31The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this [branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on the master branch. | 31The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) [on the yanqihu branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June 2020. |
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| 33The second stable micro-architecture of XiangShan is called Nanhu (南湖) [on the nanhu branch](https://github.com/OpenXiangShan/XiangShan/tree/nanhu). 34 35The current version of XiangShan, also known as Kunminghu (昆明湖), is still under development on the master branch. 36 |
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| 33The micro-architecture overview of Nanhu (南湖) is shown below. 34 35 36 37 38 39## Sub-directories Overview 40 --- 70 unchanged lines hidden (view full) --- 111 112| Sub-module | Source | Detail | 113| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ | 114| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | Our new L2/L3 design are inspired by Sifive's `block-inclusivecache`. | 115| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the Diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. | 116 117We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the [license](LICENSE). 118 | 37The micro-architecture overview of Nanhu (南湖) is shown below. 38 39 40 41 42 43## Sub-directories Overview 44 --- 70 unchanged lines hidden (view full) --- 115 116| Sub-module | Source | Detail | 117| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ | 118| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | Our new L2/L3 design are inspired by Sifive's `block-inclusivecache`. | 119| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the Diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. | 120 121We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the [license](LICENSE). 122 |
| 123## Publications 124 125### MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology 126 127Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. 128It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. 129This paper is awarded all three available badges for artifacts evaluation. 130 131[Paper PDF](https://github.com/OpenXiangShan/XiangShan-doc/blob/main/publications/micro2022-xiangshan.pdf) | IEEE Xplore (TBD) | ACM DL (TBD) | BibTeX (TBD) |
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