Makefile (b47399fbafae927f73bc47e75aad00d80540b25c) Makefile (885733f19be20791a2bd7d4c4967829a5a975334)
1TOP = TopMain
2BUILD_DIR = ./build
3TOP_V = $(BUILD_DIR)/$(TOP).v
4SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
1TOP = TopMain
2BUILD_DIR = ./build
3TOP_V = $(BUILD_DIR)/$(TOP).v
4SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
5MEM_GEN = ./scripts/vlsi_mem_gen
5
6SIMTOP = top.TestMain
7EMU_IMAGE = $(BUILD_DIR)/bin-readmemh
8IMAGE ?= temp
9NEMU_IMAGE ?= $(IMAGE)
10
11.DEFAULT_GOAL = verilog
12
13help:
14 sbt 'test:runMain top.TopMain --help'
15
16$(TOP_V): $(SCALA_FILE)
17 mkdir -p $(@D)
6
7SIMTOP = top.TestMain
8EMU_IMAGE = $(BUILD_DIR)/bin-readmemh
9IMAGE ?= temp
10NEMU_IMAGE ?= $(IMAGE)
11
12.DEFAULT_GOAL = verilog
13
14help:
15 sbt 'test:runMain top.TopMain --help'
16
17$(TOP_V): $(SCALA_FILE)
18 mkdir -p $(@D)
18 sbt 'runMain top.$(TOP) -td $(@D) --output-file $(@F)'
19 sbt 'runMain top.$(TOP) -td $(@D) --output-file $(@F) --repl-seq-mem -c:NOOPFPGA:-o:$(@D)/$(@F).conf'
20 $(MEM_GEN) $(@D)/$(@F).conf >> $@
19 sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@
20
21verilog: $(TOP_V)
22
23SIM_TOP = NOOPSimTop
24SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v
25$(SIM_TOP_V): $(SCALA_FILE)
26 mkdir -p $(@D)

--- 45 unchanged lines hidden --- 		21 sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@
22
23verilog: $(TOP_V)
24
25SIM_TOP = NOOPSimTop
26SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v
27$(SIM_TOP_V): $(SCALA_FILE)
28 mkdir -p $(@D)

--- 45 unchanged lines hidden ---