| Makefile (b280e436fa819716134eee64a45ffba44a91f704) | Makefile (a5b77de44ecd30ff2bbdebcfd07ca41d86e70db9) |
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| 1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 --- 40 unchanged lines hidden (view full) --- 49DEBUG_ARGS += $(MFC_ARGS) 50PLDM_ARGS += $(MFC_ARGS) 51else 52CHISEL_VERSION = chisel3 53FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 54SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 55endif 56 | 1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 --- 40 unchanged lines hidden (view full) --- 49DEBUG_ARGS += $(MFC_ARGS) 50PLDM_ARGS += $(MFC_ARGS) 51else 52CHISEL_VERSION = chisel3 53FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 54SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 55endif 56 |
| 57ifneq ($(XSTOP_PREFIX),) 58RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 59DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 60PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) 61endif 62 |
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| 57# co-simulation with DRAMsim3 58ifeq ($(WITH_DRAMSIM3),1) 59ifndef DRAMSIM3_HOME 60$(error DRAMSIM3_HOME is not set) 61endif 62override SIM_ARGS += --with-dramsim3 63endif 64 --- 136 unchanged lines hidden --- | 63# co-simulation with DRAMsim3 64ifeq ($(WITH_DRAMSIM3),1) 65ifndef DRAMSIM3_HOME 66$(error DRAMSIM3_HOME is not set) 67endif 68override SIM_ARGS += --with-dramsim3 69endif 70 --- 136 unchanged lines hidden --- |