| Makefile (aab688f44ace0272e27d0c55e4d138bfd3134baf) | Makefile (afbe002e3432238603f2e4de09345aba9a4510ca) |
|---|---|
| 1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 --- 45 unchanged lines hidden (view full) --- 54endif 55 56# common chisel args 57ifeq ($(MFC),1) 58CHISEL_VERSION = chisel 59FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf" 60SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf" 61MFC_ARGS = --dump-fir $(FIRTOOL_ARGS) \ | 1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 --- 45 unchanged lines hidden (view full) --- 54endif 55 56# common chisel args 57ifeq ($(MFC),1) 58CHISEL_VERSION = chisel 59FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf" 60SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf" 61MFC_ARGS = --dump-fir $(FIRTOOL_ARGS) \ |
| 62 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing" | 62 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" |
| 63RELEASE_ARGS += $(MFC_ARGS) 64DEBUG_ARGS += $(MFC_ARGS) 65PLDM_ARGS += $(MFC_ARGS) 66else 67CHISEL_VERSION = chisel3 68FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 69SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 70endif --- 19 unchanged lines hidden (view full) --- 90# dynamic switch CONSTANTIN 91ifeq ($(WITH_CONSTANTIN),0) 92$(info disable WITH_CONSTANTIN) 93else 94override SIM_ARGS += --with-constantin 95endif 96 97# emu for the release version | 63RELEASE_ARGS += $(MFC_ARGS) 64DEBUG_ARGS += $(MFC_ARGS) 65PLDM_ARGS += $(MFC_ARGS) 66else 67CHISEL_VERSION = chisel3 68FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 69SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 70endif --- 19 unchanged lines hidden (view full) --- 90# dynamic switch CONSTANTIN 91ifeq ($(WITH_CONSTANTIN),0) 92$(info disable WITH_CONSTANTIN) 93else 94override SIM_ARGS += --with-constantin 95endif 96 97# emu for the release version |
| 98RELEASE_ARGS += --disable-all --remove-assert --fpga-platform | 98RELEASE_ARGS += --fpga-platform --disable-always-basic-diff --disable-perf |
| 99DEBUG_ARGS += --enable-difftest 100PLDM_ARGS += --disable-all --fpga-platform 101ifeq ($(RELEASE),1) 102override SIM_ARGS += $(RELEASE_ARGS) 103else ifeq ($(PLDM),1) 104override SIM_ARGS += $(PLDM_ARGS) 105else 106override SIM_ARGS += $(DEBUG_ARGS) --- 94 unchanged lines hidden --- | 99DEBUG_ARGS += --enable-difftest 100PLDM_ARGS += --disable-all --fpga-platform 101ifeq ($(RELEASE),1) 102override SIM_ARGS += $(RELEASE_ARGS) 103else ifeq ($(PLDM),1) 104override SIM_ARGS += $(PLDM_ARGS) 105else 106override SIM_ARGS += $(DEBUG_ARGS) --- 94 unchanged lines hidden --- |