| Makefile (9eee369fad937ed93672d4514861f79317ecc9f5) | Makefile (d7a3496cea0b4b2142fa78a7cda036c984d3671c) |
|---|---|
| 1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 --- 107 unchanged lines hidden (view full) --- 116override SIM_ARGS += $(RELEASE_ARGS) 117else ifeq ($(PLDM),1) 118override SIM_ARGS += $(PLDM_ARGS) 119else 120override SIM_ARGS += $(DEBUG_ARGS) 121endif 122 123TIMELOG = $(BUILD_DIR)/time.log | 1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 --- 107 unchanged lines hidden (view full) --- 116override SIM_ARGS += $(RELEASE_ARGS) 117else ifeq ($(PLDM),1) 118override SIM_ARGS += $(PLDM_ARGS) 119else 120override SIM_ARGS += $(DEBUG_ARGS) 121endif 122 123TIMELOG = $(BUILD_DIR)/time.log |
| 124TIME_CMD = time -a -o $(TIMELOG) | 124TIME_CMD = time -avp -o $(TIMELOG) |
| 125 126SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' 127 128ifeq ($(PLDM),1) 129SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 130SED_ENDIF = `endif // not def SYNTHESIS 131endif 132 --- 19 unchanged lines hidden (view full) --- 152 @cat .__head__ .__diff__ $@ > .__out__ 153 @mv .__out__ $@ 154 @rm .__head__ .__diff__ 155 156verilog: $(TOP_V) 157 158$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 159 mkdir -p $(@D) | 125 126SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' 127 128ifeq ($(PLDM),1) 129SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 130SED_ENDIF = `endif // not def SYNTHESIS 131endif 132 --- 19 unchanged lines hidden (view full) --- 152 @cat .__head__ .__diff__ $@ > .__out__ 153 @mv .__out__ $@ 154 @rm .__head__ .__diff__ 155 156verilog: $(TOP_V) 157 158$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 159 mkdir -p $(@D) |
| 160 @echo "\n[mill] Generating Verilog files..." > $(TIMELOG) | 160 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) |
| 161 @date -R | tee -a $(TIMELOG) 162 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \ 163 -td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \ 164 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 165ifeq ($(MFC),1) 166 $(SPLIT_VERILOG) $(RTL_DIR) $(SIM_TOP).v 167 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)" 168endif --- 61 unchanged lines hidden --- | 161 @date -R | tee -a $(TIMELOG) 162 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \ 163 -td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \ 164 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 165ifeq ($(MFC),1) 166 $(SPLIT_VERILOG) $(RTL_DIR) $(SIM_TOP).v 167 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)" 168endif --- 61 unchanged lines hidden --- |