| Makefile (5bd65c56355db1d4f5b92a3815df78273c01b892) | Makefile (907d5012b917b90454f8ecef372b3e5d9b03c368) |
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| 1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: --- 81 unchanged lines hidden (view full) --- 90# configuration from yaml file 91ifneq ($(YAML_CONFIG),) 92COMMON_EXTRA_ARGS += --yaml-config $(YAML_CONFIG) 93endif 94 95# public args sumup 96RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 97DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) | 1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: --- 81 unchanged lines hidden (view full) --- 90# configuration from yaml file 91ifneq ($(YAML_CONFIG),) 92COMMON_EXTRA_ARGS += --yaml-config $(YAML_CONFIG) 93endif 94 95# public args sumup 96RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 97DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) |
| 98PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) | 98override PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) |
| 99 100# co-simulation with DRAMsim3 101ifeq ($(WITH_DRAMSIM3),1) 102ifndef DRAMSIM3_HOME 103$(error DRAMSIM3_HOME is not set) 104endif 105override SIM_ARGS += --with-dramsim3 106endif --- 26 unchanged lines hidden (view full) --- 133# dynamic switch CONSTANTIN 134ifeq ($(WITH_CONSTANTIN),1) 135override SIM_ARGS += --with-constantin 136endif 137 138# emu for the release version 139RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 140DEBUG_ARGS += --enable-difftest | 99 100# co-simulation with DRAMsim3 101ifeq ($(WITH_DRAMSIM3),1) 102ifndef DRAMSIM3_HOME 103$(error DRAMSIM3_HOME is not set) 104endif 105override SIM_ARGS += --with-dramsim3 106endif --- 26 unchanged lines hidden (view full) --- 133# dynamic switch CONSTANTIN 134ifeq ($(WITH_CONSTANTIN),1) 135override SIM_ARGS += --with-constantin 136endif 137 138# emu for the release version 139RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 140DEBUG_ARGS += --enable-difftest |
| 141PLDM_ARGS += --fpga-platform --enable-difftest | 141override PLDM_ARGS += --enable-difftest |
| 142ifeq ($(RELEASE),1) 143override SIM_ARGS += $(RELEASE_ARGS) 144else ifeq ($(PLDM),1) 145override SIM_ARGS += $(PLDM_ARGS) 146else 147override SIM_ARGS += $(DEBUG_ARGS) 148endif 149 | 142ifeq ($(RELEASE),1) 143override SIM_ARGS += $(RELEASE_ARGS) 144else ifeq ($(PLDM),1) 145override SIM_ARGS += $(PLDM_ARGS) 146else 147override SIM_ARGS += $(DEBUG_ARGS) 148endif 149 |
| 150# use RELEASE_ARGS for TopMain by default 151ifeq ($(PLDM), 1) 152TOPMAIN_ARGS += $(PLDM_ARGS) 153else 154TOPMAIN_ARGS += $(RELEASE_ARGS) 155endif 156 |
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| 150TIMELOG = $(BUILD_DIR)/time.log 151TIME_CMD = time -avp -o $(TIMELOG) 152 153ifeq ($(PLDM),1) 154SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 155SED_ENDIF = `endif // not def SYNTHESIS 156endif 157 --- 10 unchanged lines hidden (view full) --- 168 169test-jar: 170 mill -i xiangshan.test.assembly 171 172$(TOP_V): $(SCALA_FILE) 173 mkdir -p $(@D) 174 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 175 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ | 157TIMELOG = $(BUILD_DIR)/time.log 158TIME_CMD = time -avp -o $(TIMELOG) 159 160ifeq ($(PLDM),1) 161SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 162SED_ENDIF = `endif // not def SYNTHESIS 163endif 164 --- 10 unchanged lines hidden (view full) --- 175 176test-jar: 177 mill -i xiangshan.test.assembly 178 179$(TOP_V): $(SCALA_FILE) 180 mkdir -p $(@D) 181 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 182 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ |
| 176 --num-cores $(NUM_CORES) $(RELEASE_ARGS) | 183 --num-cores $(NUM_CORES) $(TOPMAIN_ARGS) |
| 177ifeq ($(CHISEL_TARGET),systemverilog) 178 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 179 @git log -n 1 >> .__head__ 180 @git diff >> .__diff__ 181 @sed -i 's/^/\/\// ' .__head__ 182 @sed -i 's/^/\/\//' .__diff__ 183 @cat .__head__ .__diff__ $@ > .__out__ 184 @mv .__out__ $@ --- 89 unchanged lines hidden --- | 184ifeq ($(CHISEL_TARGET),systemverilog) 185 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 186 @git log -n 1 >> .__head__ 187 @git diff >> .__diff__ 188 @sed -i 's/^/\/\// ' .__head__ 189 @sed -i 's/^/\/\//' .__diff__ 190 @cat .__head__ .__diff__ $@ > .__out__ 191 @mv .__out__ $@ --- 89 unchanged lines hidden --- |