Makefile (54cc3a061d25ca2e64b2828dd96ba54d6f2f2cf2) Makefile (2993c5ecece73b73073301e23435ca1b763d0b5f)
1#***************************************************************************************
1#***************************************************************************************
2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
3# Copyright (c) 2020-2021 Peng Cheng Laboratory
4#
5# XiangShan is licensed under Mulan PSL v2.
6# You can use this software according to the terms and conditions of the Mulan PSL v2.
7# You may obtain a copy of Mulan PSL v2 at:
8# http://license.coscl.org.cn/MulanPSL2
9#
10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,

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118override SIM_ARGS += $(PLDM_ARGS)
119else
120override SIM_ARGS += $(DEBUG_ARGS)
121endif
122
123TIMELOG = $(BUILD_DIR)/time.log
124TIME_CMD = time -avp -o $(TIMELOG)
125
4# Copyright (c) 2020-2021 Peng Cheng Laboratory
5#
6# XiangShan is licensed under Mulan PSL v2.
7# You can use this software according to the terms and conditions of the Mulan PSL v2.
8# You may obtain a copy of Mulan PSL v2 at:
9# http://license.coscl.org.cn/MulanPSL2
10#
11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,

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119override SIM_ARGS += $(PLDM_ARGS)
120else
121override SIM_ARGS += $(DEBUG_ARGS)
122endif
123
124TIMELOG = $(BUILD_DIR)/time.log
125TIME_CMD = time -avp -o $(TIMELOG)
126
126SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g'
127
128ifeq ($(PLDM),1)
129SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala
130SED_ENDIF = `endif // not def SYNTHESIS
131endif
132
133.DEFAULT_GOAL = verilog
134
135help:
136 mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help
137
138$(TOP_V): $(SCALA_FILE)
139 mkdir -p $(@D)
140 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \
141 --target-dir $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \
142 --num-cores $(NUM_CORES) $(RELEASE_ARGS)
143ifeq ($(MFC),1)
144 $(SPLIT_VERILOG) $(RTL_DIR) $(TOP).v
145 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(RTL_DIR)"
146endif
127ifeq ($(PLDM),1)
128SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala
129SED_ENDIF = `endif // not def SYNTHESIS
130endif
131
132.DEFAULT_GOAL = verilog
133
134help:
135 mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help
136
137$(TOP_V): $(SCALA_FILE)
138 mkdir -p $(@D)
139 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \
140 --target-dir $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \
141 --num-cores $(NUM_CORES) $(RELEASE_ARGS)
142ifeq ($(MFC),1)
143 $(SPLIT_VERILOG) $(RTL_DIR) $(TOP).v
144 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(RTL_DIR)"
145endif
147 $(SED_CMD) $@
148 @git log -n 1 >> .__head__
149 @git diff >> .__diff__
150 @sed -i 's/^/\/\// ' .__head__
151 @sed -i 's/^/\/\//' .__diff__
152 @cat .__head__ .__diff__ $@ > .__out__
153 @mv .__out__ $@
154 @rm .__head__ .__diff__
155

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161 @date -R | tee -a $(TIMELOG)
162 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \
163 --target-dir $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \
164 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace
165ifeq ($(MFC),1)
166 $(SPLIT_VERILOG) $(RTL_DIR) $(SIM_TOP).v
167 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)"
168endif
146 @git log -n 1 >> .__head__
147 @git diff >> .__diff__
148 @sed -i 's/^/\/\// ' .__head__
149 @sed -i 's/^/\/\//' .__diff__
150 @cat .__head__ .__diff__ $@ > .__out__
151 @mv .__out__ $@
152 @rm .__head__ .__diff__
153

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159 @date -R | tee -a $(TIMELOG)
160 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \
161 --target-dir $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \
162 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace
163ifeq ($(MFC),1)
164 $(SPLIT_VERILOG) $(RTL_DIR) $(SIM_TOP).v
165 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)"
166endif
169 $(SED_CMD) $@
170 @git log -n 1 >> .__head__
171 @git diff >> .__diff__
172 @sed -i 's/^/\/\// ' .__head__
173 @sed -i 's/^/\/\//' .__diff__
174 @cat .__head__ .__diff__ $@ > .__out__
175 @mv .__out__ $@
176 @rm .__head__ .__diff__
177ifeq ($(PLDM),1)

--- 59 unchanged lines hidden --- 		167 @git log -n 1 >> .__head__
168 @git diff >> .__diff__
169 @sed -i 's/^/\/\// ' .__head__
170 @sed -i 's/^/\/\//' .__diff__
171 @cat .__head__ .__diff__ $@ > .__out__
172 @mv .__out__ $@
173 @rm .__head__ .__diff__
174ifeq ($(PLDM),1)

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