Makefile - OpenGrok cross reference for /XiangShan/Makefile

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Makefile (18179bb94b8c149c762736130fe066de348c6f60)	Makefile (720dd6218ef4045360a23b552db1137cbb6e6e59)
1#************************************************************************************* 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: --- 20 unchanged lines hidden** (view full) --- 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36	1#************************************************************************************* 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: --- 20 unchanged lines hidden** (view full) --- 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36
37IMAGE ?= temp
38CONFIG ?= DefaultConfig 39NUM_CORES ?= 1 40MFC ?= 1 41	37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39MFC ?= 1 40
	41ifneq ($(shell echo "$(MAKECMDGOALS)" \| grep ' '),) 42$(error At most one target can be specified) 43endif
42 43ifeq ($(MAKECMDGOALS),) 44GOALS = verilog 45else 46GOALS = $(MAKECMDGOALS) 47endif 48 49# common chisel args --- 13 unchanged lines hidden (view full) --- 63endif 64 65ifneq ($(XSTOP_PREFIX),) 66RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 67DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 68PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) 69endif 70	44 45ifeq ($(MAKECMDGOALS),) 46GOALS = verilog 47else 48GOALS = $(MAKECMDGOALS) 49endif 50 51# common chisel args --- 13 unchanged lines hidden (view full) --- 65endif 66 67ifneq ($(XSTOP_PREFIX),) 68RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 69DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 70PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) 71endif 72
	73ifeq ($(IMSIC_USE_TL),1) 74RELEASE_ARGS += --imsic-use-tl 75DEBUG_ARGS += --imsic-use-tl 76PLDM_ARGS += --imsic-use-tl 77endif 78
71# co-simulation with DRAMsim3 72ifeq ($(WITH_DRAMSIM3),1) 73ifndef DRAMSIM3_HOME 74$(error DRAMSIM3_HOME is not set) 75endif 76override SIM_ARGS += --with-dramsim3 77endif 78 --- 56 unchanged lines hidden (view full) --- 135 mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help 136 137$(TOP_V): $(SCALA_FILE) 138 mkdir -p $(@D) 139 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \ 140 --target-dir $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \ 141 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 142ifeq ($(MFC),1)	79# co-simulation with DRAMsim3 80ifeq ($(WITH_DRAMSIM3),1) 81ifndef DRAMSIM3_HOME 82$(error DRAMSIM3_HOME is not set) 83endif 84override SIM_ARGS += --with-dramsim3 85endif 86 --- 56 unchanged lines hidden (view full) --- 143 mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help 144 145$(TOP_V): $(SCALA_FILE) 146 mkdir -p $(@D) 147 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \ 148 --target-dir $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \ 149 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 150ifeq ($(MFC),1)
143 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(RTL_DIR)"	151 $(MEM_GEN_SEP) "$(MEM_GEN)" "$@.conf" "$(@D)"
144endif 145 @git log -n 1 >> .__head__ 146 @git diff >> .__diff__ 147 @sed -i 's/^/\/\// ' .__head__ 148 @sed -i 's/^/\/\//' .__diff__ 149 @cat .__head__ .__diff__ $@ > .__out__ 150 @mv .__out__ $@ 151 @rm .__head__ .__diff__ 152 153verilog: $(TOP_V) 154 155$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 156 mkdir -p $(@D) 157 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 158 @date -R \| tee -a $(TIMELOG) 159 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \ 160 --target-dir $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \ 161 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 162ifeq ($(MFC),1)	152endif 153 @git log -n 1 >> .__head__ 154 @git diff >> .__diff__ 155 @sed -i 's/^/\/\// ' .__head__ 156 @sed -i 's/^/\/\//' .__diff__ 157 @cat .__head__ .__diff__ $@ > .__out__ 158 @mv .__out__ $@ 159 @rm .__head__ .__diff__ 160 161verilog: $(TOP_V) 162 163$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 164 mkdir -p $(@D) 165 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 166 @date -R \| tee -a $(TIMELOG) 167 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \ 168 --target-dir $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \ 169 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 170ifeq ($(MFC),1)
163 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)"	171 $(MEM_GEN_SEP) "$(MEM_GEN)" "$@.conf" "$(@D)"
164endif 165 @git log -n 1 >> .__head__ 166 @git diff >> .__diff__ 167 @sed -i 's/^/\/\// ' .__head__ 168 @sed -i 's/^/\/\//' .__diff__ 169 @cat .__head__ .__diff__ $@ > .__out__ 170 @mv .__out__ $@ 171 @rm .__head__ .__diff__ --- 51 unchanged lines hidden (view full) --- 223pldm-run: 224 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 225 226pldm-debug: 227 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 228 229include Makefile.test 230	172endif 173 @git log -n 1 >> .__head__ 174 @git diff >> .__diff__ 175 @sed -i 's/^/\/\// ' .__head__ 176 @sed -i 's/^/\/\//' .__diff__ 177 @cat .__head__ .__diff__ $@ > .__out__ 178 @mv .__out__ $@ 179 @rm .__head__ .__diff__ --- 51 unchanged lines hidden (view full) --- 231pldm-run: 232 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 233 234pldm-debug: 235 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 236 237include Makefile.test 238
	239include src/main/scala/device/standalone/standalone_device.mk 240
231.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO)	241.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO)